The present disclosure relates to an internal voltage generation circuit, and more particularly to an internal voltage generation circuit which is capable of reducing power consumption in a power down mode.
Generally, in a dynamic random access memory (DRAM), a power down mode Powerdown is supported in which the operations of an internal clock and a buffer are stopped in response to a clock enable signal CKE to drop power consumption to a predetermined level or lower. The power down mode becomes a main issue, particularly in mobile fields including a mobile phone, personal digital assistant (PDA), etc., because it is important in the mobile fields to reduce power consumption.
In the case of an internal voltage Vperi which is supplied to a peri area, it is preferred, in consideration of speed characteristics, to use a voltage of the same level as that of an external voltage Vdd, as the internal voltage Vperi. However, the use of the internal voltage Vperi of the same level as that of the external voltage Vdd results in leakage current increasing as the external voltage Vdd increases.
On the other hand, in order to avoid leakage current, a voltage of a level lower than that of the external voltage Vdd may be used as the internal voltage Vperi. In this case, there is another problem that speed characteristics of the respective circuits deteriorate due to the level down of internal operating voltages.